1. Field of the Invention
The present invention relates to a high speed amplifier and a comparator using the same applied to a sequential successive approximation analog-to-digital (A/D) converter.
2. Description of the Related Art
Generally, A/D converters are required to accurately convert an analog signal into a digital signal at high speed.
One typical A/D converter is a sequential successive approximation A/D converter which is constructed by a comparator for comparing an input voltage with a reference voltage derived from an input analog voltage, a sequential approximation register (SAR), a digital-to-analog (D/A) converter for performing a D/A conversion upon the content of the sequential approximation register to generate the input voltage, and a control circuit for controlling the content of the sequential approximation register in accordance with the output signal of the comparator. This will be explained later in detail.
A first prior art comparator is constructed by a plurality of cascaded fast amplifiers of a two-input and two-output type with a low gain (amplification) and a low output impedance operable at high speed, and a slow amplifier of a two-input and one-output type with a high gain (amplification) and a high output impedance operable at low speed (see: FIG. 7 of JP-10-200385A). This also will be explained later in detail.
In the above-described first prior art comparator, however, when the input voltage crosses the reference voltage, one return delay time is caused by each of the fast amplifiers, so that the total delay time would be increased. Also, the operation speed of the fast amplifiers per se cannot be increased. Thus, the first prior art comparator cannot be operated at a high speed.
In a second prior art comparator, switches are provided at the output ends of each of the fast amplifiers of the first prior art comparator (see: FIGS. 1 and 2 of JP-10-200385A). As a result, every time a stable time period has passed after one comparison operation, the above-mentioned switches are turned ON, so that the output voltages of the fast amplifiers are initialized or reset to their operating points. Therefore, since no return delay times are generated, the total delay time is not increased. Thus, the second prior art comparator may be operated at high speed. This also will be explained later in detail.